NXP Semiconductors /MIMXRT1011 /PWM1 /SM2STS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SM2STS

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMPF_0)CMPF0 (CFX0)CFX0 0 (CFX1)CFX1 0 (CFB0)CFB0 0 (CFB1)CFB1 0 (CFA0)CFA0 0 (CFA1)CFA1 0 (RF_0)RF 0 (REF_0)REF 0 (RUF_0)RUF

RUF=RUF_0, CMPF=CMPF_0, RF=RF_0, REF=REF_0

Description

Status Register

Fields

CMPF

Compare Flags

0 (CMPF_0): No compare event has occurred for a particular VALx value.

1 (CMPF_1): A compare event has occurred for a particular VALx value.

CFX0

Capture Flag X0

CFX1

Capture Flag X1

CFB0

Capture Flag B0

CFB1

Capture Flag B1

CFA0

Capture Flag A0

CFA1

Capture Flag A1

RF

Reload Flag

0 (RF_0): No new reload cycle since last STS[RF] clearing

1 (RF_1): New reload cycle since last STS[RF] clearing

REF

Reload Error Flag

0 (REF_0): No reload error occurred.

1 (REF_1): Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.

RUF

Registers Updated Flag

0 (RUF_0): No register update has occurred since last reload.

1 (RUF_1): At least one of the double buffered registers has been updated since the last reload.

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